Conventional transistors are fabricated horizontally. Prior art vertical channel transistors use epitaxial silicon (epi Si) as the vertical channel.
U.S. Pat. No. 5,757,038 to Tiwari et al. describes a silicon germanium (SiGe) vertical channel within a dual gate field effect transistor (FET).
U.S. Pat. No. 4,740,826 to Chatterjee describes a vertical transistor (Tx) with a tungsten (W) gate and doped epitaxial channel.
U.S. Pat. No. 5,981,318 to Blanchard describes a SiGe channel for a horizontal Tx.
U.S. Pat. No. 5,780,327 to Chu et al. describes a vertical double gate FET with a W gate and vertical channel.
The xe2x80x9cGrowth and characterization of strained Si1xe2x88x92xGex multi-quantum well waveguide photodetectors on (110) Si for 1.3 and 1.55 xcexcm,xe2x80x9d Bernhard-Hxc3x6fer et al., Physica E, Vol. 2, Issue 1-4; Jul. 15, 1998, article describes the growth of pseudomorphic Si1xe2x88x92xGex multi-quantum well p-i-n photodiodes on (110) Si by molecular beam epitaxy.
Accordingly, it is an object of the present invention to provide a method of fabricating a vertical channel transistor having a higher carrier mobility.
Another object of the present invention is to provide a method of fabricating a vertical channel SiGe multi-quantum well transistor having improved performance.
A further object of the present invention is to provide a method of fabricating a vertical channel transistor with a strained layer super lattice having improved carrier mobility.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Silicon dioxide (oxide) is deposited to fill the isolation trenches followed by chemical mechanical planarization. The oxide is etched to form a gate trench within one of the trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. SiGe multi-quantum wells are formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells and within the gate trench. A gate conductor layer is formed on the gate dielectric layer, filling the gate trench.